Integrated Circuits - A Brief History

Very brief, and incomplete, but I’ll add to it as I go. In the beginning (the 1970s), CPUs shipped in Dual In-line Package (“DIP”) packaging:

DIP

These were ubiquitous in the late 70s and early 80s, but they became impractical above 40 pins, which led to some interesting design compromises, like the 24-bit address bus and 16-bit external data bus of the Motorola 68000:

But these could be through-hole mounted, or socketed, and it was what it was. Following that, we start getting into interesting diversions, like 68-pin PLCC (Plastic Leaded Chip Carrier) and 68-pin Ceramic LCC (Lead Less Chip Carrier) packages, commonly seen on the 80286, starting in the early 1980s:

PLCC

CLCC

Starting more-or-less around the era of the 80386 and the 68030, came Pin Grid Array, used for, e.g., socketed (and through-hole soldered) CPUs through the mid-2000s at least, when Intel switched to Land Grid Array (LGA) for the Pentium 4 (and a couple of years later, moved Xeon over) (AMD still uses PGA for many CPUs):

PGA

There was also a detour into slot packaging (i.e., Single Edge Contact Cartridge (SECC)), Intel’s Slot 1 and AMD’s Slot A. Intel move to Slot 1 officially to move L2 cache closer to the CPU, but also probably in large part to exclude AMD and other competitors, who were releasing chips (AMD K5, Cyrix 6x86, etc) that could sit in the same “socket 7” boards as Intel’s Pentium chips. Example:

Then there’s QFP (Quad Flat Package) (and the related TQFP (Thin Quad Flat Package), which are surface-mount technologies used often in embedded systems, laptops and portable digital assistant (PDA) devices like the Palm Pilot, etc., in the 1990s and into the 2000s:

TQFP

More later...